Intel, Samsung and TSMC demonstrate 3D stacked transistors

 

【Lansheng Technology News】At this week's IEEE International Electronic Devices Conference, TSMC demonstrated their understanding of CFETs, the logic stack used in CMOS chips. CFET is a structure that stacks together two types of transistors required for CMOS logic. At this week's IEEE International Electronic Devices Conference in San Francisco, Intel, Samsung and TSMC showed off their progress on the next evolution of transistors.

Intel inverter

Intel was one of the first three companies to demonstrate CFET, showing an early version back at IEDM 2020. This time, Intel reports several improvements to one of the simplest circuits made with CFETs, the inverter. A CMOS inverter sends the same input voltage to the gates of both devices in the stack and produces an output that is logically the opposite of the input.

Additionally, Intel improved the performance by increasing the number of nanosheets per device from two to three, reducing the distance between the two devices from 50 nanometers to 30 nanometers, and using improved connector geometry. Electrical properties of CFET stack.

Samsung’s secret weapon

Samsung is even smaller than Intel, showing results for contact polymer pitch (CPP) of 48nm and 45nm, compared to Intel's 60nm CPP, although these results are for individual devices rather than complete inverters. Although the performance of the smaller of Samsung's two prototype CFETs has declined, but not by much, the company's researchers believe optimization of the manufacturing process will resolve the issue.

Key to Samsung's success is the ability to electrically isolate the sources and drains of stacked pFET and nFET devices. If there is insufficient isolation, the devices, which Samsung calls 3D stacked FETs (3DSFETs), will leak current. A key step in achieving this isolation is to replace wet etching with a new type of dry etching involving wet chemicals. This resulted in an 80% increase in good device yield.

Like Intel, Samsung touches the bottom of the device from underneath the silicon to save space. However, the Korean chipmaker differs from the U.S. company in that it uses a single nanosheet in each paired device instead of Intel's three. According to the company's researchers, increasing the number of nanosheets will improve the performance of CFETs.

TSMC tries

Like Samsung, TSMC has managed to reach industrially relevant 48nm. Features of the device include a new method of forming a dielectric layer between the top and bottom devices to keep them isolated. Nanosheets are typically formed from alternating layers of silicon and silicon germanium. At appropriate steps in the process, silicon germanium-specific etching methods remove the material, releasing silicon nanowires. To create an isolation layer between the two devices, TSMC uses silicon germanium and has an unusually high content of silicon germanium in this layer, knowing that it corrodes faster than other SiGe layers. In this way, the isolation layer can be built in several steps before releasing the silicon nanowires.

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